Wafer with intrinsic semiconductor layer

ABSTRACT

The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method.

FIELD OF INVENTION

The present invention relates to fully depleted CMOS devices, inparticular, wafers for the manufacture of embedded DRAM devices andco-integrated on the same piece of substrate, fully depleted SOItransistors with back biasing capability, wherein the wafers compriseintrinsic semiconductor layers.

BACKGROUND OF THE INVENTION

Semiconductor-On-Insulator (SeOI) and, in particular,Silicon-On-Insulator (SOI) semiconductor devices are of increasinginterest in present and future semiconductor manufacturing, for example,in the context of the Complementary Metal Oxide Semiconductor (CMOS)technology.

Embedded DRAM devices become increasingly important for high-performanceCMOS electronics, since compared to conventional SRAMs the packagedensity can be significantly increased. Besides the high integrationlower noise and power consumption as well as higher bandwidth can beachieved as compared to external SRAM/DRAM architectures. In addition,planar fully depleted SOI transistors represent a cost effectiveapproach with respect to the scaling of transistor devices. Planar fullydepleted SOI transistors advantageously allow for back biasing in orderto adjust the threshold voltage to reduce leakage power and/or boostperformances. With Back Bias VI can be changed dynamically. Relativelythin buried oxide (BOX) layers, for example, with a thickness in therange of 5 to 50 nm, are necessary to provide optimal back biasingbenefit.

It is known to manufacture embedded DRAMs based on wafers with apre-doped n-layer formed in the handle substrates, directly underneaththe BOX and rather thick to contain the entire DRAM capacitor trench,typically several microns. For example, a phosphorous n⁺ layer with aconcentration of 10¹⁹ cm⁻³ may serve as a capacitor bottom plate. The n⁺layer is crucial in terms of scaling of the eDRAMs. However, therearises a problem when a logic part comprising back-biased planar fullyor partially depleted SOL transistors shall be integrated together withembedded DRAMs, since the pre-doped n⁺ layer heavily hampers themanufacture of the back-biasing features. Back bias regions must beelectrically insulated one from another in order for them to be biasedat different voltages without high leakage current. To achieve thatinsulation, we will need reverse-biased junctions on the current pathfrom one back bias region to another. We will typically have N and Players on top of the handle substrate creating the need junctions, andcut then vertically by STI structures to insulate one region from theothers.

Such multilayer structure can potentially be manufactured starting withthe thick N+ layer required for the eDRAM, but would require highimplantation doses to be implanted through the SOI and BOX layers. Thisis not desirable because it might create defects and also dope the SOIlayer,

In view of this, it is a problem underlying the present invention toprovide a method for the integrated manufacture of both embedded DRAMSand back-biased transistors.

SUMMARY OF THE INVENTION

In order to address the above-mentioned problem, it is provided a methodfor the manufacture of a wafer, comprising the steps of providing (e.g.,by forming) a doped layer on a semiconductor substrate; providing (e.g.,by forming) a first semiconductor layer on the doped layer; providing(e.g., by forming) an oxide layer on the first semiconductor layer; andproviding (e.g., by forming) a second semiconductor layer on the oxidelayer to form a wafer having a buried oxide layer and a doped layerbeneath the buried oxide layer.

The process results in a wafer comprising a semiconductor substrate; adoped layer upon the semiconductor substrate; a first semiconductorlayer upon the semiconductor substrate; an oxide layer formed upon thefirst semiconductor layer; and a second semiconductor layer formed uponthe buried oxide layer, thus providing a wafer having a buried oxidelayer and a doped layer beneath the buried oxide layer.

The thus provided wafer facilitates the manufacture of an embedded DRAMintegrated together with a logic part comprising SOI transistors thatare back-biased for control of the threshold voltage. Contrary to theart there is no need for any complicated processing of a conventionalwafer for preparation for the formation of back-biasing regions requiredby the provision of the heavily doped embedded doped layer, Rather, theprovision of the first (intrinsic) semiconductor layer allows for easyconversion into n or p doped back-biasing regions for the SOLtransistors of the logic part enabling a first level of Vt tuning bychanging the back bias region doping between N or P.

According to particular examples, the substrate is made of or comprises(poly- or mono) silicon. Both the first and the second semiconductorlayer may comprise or consist of silicon, The buried oxide. layer maycomprise an SiO₂ compound. The doped layer may, for example, be n⁺ dopedsilicon, for example, silicon comprising phosphorus dopants. Theconcentration of such phosphorus dopants may be in the range of some10¹⁸ to 10²⁰ cm⁻³, in particular, about 10¹⁹ cm⁻³.

As far as the thicknesses of the individual layers of the provided waferconcerns the following choices are, for example, suitable: The thicknessof the first semiconductor layer may be in the range of 10 to 300 nm, inparticular, 50 to 150 nm. The thickness of the second semiconductorlayer may be in the range of 5 to 100 nm, in particular, 5 to 20 nm, Anextra thin second semiconductor layer (5 to 15 nm) may be provided, if afully depleted SOI transistor shall be formed in a logic part of thewafer. A somewhat thicker second semiconductor layer (up to some 100 nm)may be provided, if a partially depleted SOI transistor shall be formedin a logic part of the wafer. The thickness of the buried oxide layermay be in the range of 5 to 200 nm, in particular, 5 to 25 nm and thethickness of the doped layer may be in the range of 1 to 10 μm.

According to an embodiment the wafer may be manufactured on the basis ofsome wafer transfer process, for instance, a wafer transfer processcomprising the Smart Cut© process. The doped layer and the firstsemiconductor layer may be grown on the semiconductor substrate and thesecond semiconductor layer may be grown on a donor substrate and thewafer may be obtained by bonding the first and the second semiconductorlayers by the buried oxide layer and detaching the donor substrate.

In some detail, the manufacture of the wafer according to an examplecomprises the steps of growing the epitaxial doped layer on thesemiconductor substrate and growing the first semiconductor epitaxiallayer on the doped layer. The above-mentioned step of forming the secondsemiconductor layer on the buried oxide layer may comprise growing thesecond semiconductor layer on a donor substrate to obtain a donor wafer;forming a first oxide layer on the second semiconductor layer grown onthe donor substrate; and/or forming a second oxide layer on theepitaxial first semiconductor layer grown on the doped layer; andbonding the donor wafer to the epitaxial first semiconductor layer grownon the doped layer by the first and/or second intermediate buried layer,wherein the first and/or second oxide layer form the buried oxide layer,and removing the donor substrate. Thus, the oxide layer can be providedon either or both of the semiconductor layers to facilitate bonding ofthe layers together. Thereafter, a portion of the donor substrate can beremoved by any one of a number of processes, including grinding,polishing, etching or detaching. Detaching may be achieved by heatingthe donor substrate after providing a weakened zone therein, or by theapplication of a mechanical force or by a laser lift-off technique. Thegenerally known Smart Cut® process or a variation thereof is thepreferred way of removing the remainder of the donor substrate totransfer the second semiconductor layer and, when present, an exposedoxide layer upon it to the first semiconductor layer or when present theexposed oxide layer upon that layer. In such a manner, the desired wafercan reliably be formed avoiding significant defects of the semiconductorlayers.

The method for the manufacture of a wafer may further comprise doping atleast a region of the first semiconductor layer by n or p dopants. Forexample, some predoping of the first semiconductor layer during thegrowth of the same on the substrate can he performed. Predoping in aconcentration of about 10¹⁸ cm⁻³ might he performed. Further dopingmight be performed in later processing steps when an embedded DRAMtogether with a logic part comprising back-biased transistors ismanufactured based on the provided wafer.

The above-described examples of the inventive wafer can be used for themanufacture of a semiconductor device comprising an embedded DRAM devicein a first region of the wafer and a back-biased transistor in a secondregion of the wafer. In particular, it is provided a method for themanufacture of a semiconductor device, comprising the steps of providinga wafer obtained by a method according to one of the herein -describedexamples; forming an embedded DRAM device in a first region (DRAM part)of the wafer comprising forming a capacitor trench extending from thesecond semiconductor layer at least partly into the doped layer; andforming a back-biased transistor in a second region (logic part) of thewafer that is separated from the first region by a shallow trenchisolation and comprising forming a back-biasing region in the firstsemiconductor layer. The formation of the back-biasing region mayparticularly comprise doping of the first semiconductor layer of thewafer after it has been provided in accordance to one of theabove-described examples.

By this method an embedded DRAM device can readily be manufactured thatcomprises both a capacitor bottom plate for the DRAM in form of therelatively heavily doped layer below the first (intrinsic) semiconductorlayer and a back-biasing region for an SOI transistor formed in thefirst (intrinsic) semiconductor layer.

Furthermore, herein it is provided semiconductor device, comprising awafer provided in accordance with one of the herein-described examples;and integrated on that wafer, .an embedded DRAM device comprising acapacitor trench extending from the second semiconductor layer at leastpartly into the doped layer and a control FET having a channel region inthe second semiconductor layer; and a back-biased SOI transistorcomprising a channel region in the second semiconductor layer and adoped back-biasing region in the first semiconductor layer and a contactfor biasing the doped back-biasing region.

According to an example, in the provided semiconductor device the firstsemiconductor layer is doped in an upper region adjacent to the buriedoxide layer and undoped in a lower region adjacent to the doped layer.By doping an upper surface region of the first semiconductor layer onlya sufficiently high resistivity in the lower region between tworespective contacts that may be provided for back-biasing two differenttransistors in the logic part of the semiconductor device is guaranteed.

The semiconductor device may comprise a number of back-biased SOItransistors separated from each other and from the embedded DRAM deviceby shallow trench isolations extending from the second semiconductorlayer at least pa into the doped layer or into the semiconductorsubstrate. Both the control FET and the back-biased transistors may beprovided as fully depleted or partially depleted transistor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional features and advantages of the present invention will bedescribed with reference to the drawings. In the description, referenceis made to the accompanying figures that are meant to illustratepreferred embodiments of the invention. It is understood that suchembodiments do not represent the full scope of the invention.

FIG. 1 illustrates an example for the method for manufacturing a wafercomprising an intrinsic semiconductor layer according to the presentinvention,

FIG. 2 illustrates an embedded DRAM device integrated with back-biasedSOI transistors of a logic part manufactured on the basis on the waferillustrated in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A particular example for manufacturing a wafer in accordance with thepresent invention will now be described with reference to FIG. 1. In adonor substrate 1 a nucleation layer 2 is formed by the implantation ofions. The implantation of ions results in a weakened zone at the mainconcentration of the implanted ions. The implantation energy may be in arange of some 5 key to 20 keV and the implantation dose may be chosen tobe in the range of 5×10¹⁶ to 10¹⁷ ions/cm ², for example. A siliconlayer 3 is formed on the donor substrate 1. Subsequently, an oxide layer4 is formed atop of the silicon layer 3. Another substrate 5, forexample, a silicon substrate 5 is provided. A doped layer 6, forexample, a silicon layer doped with phosphorus dopants of aconcentration of 10¹⁹ cm⁻³ , is formed on the silicon substrate 5. Asilicon layer 7 is formed on the doped layer 6. For example, siliconlayer 7 can be grown by epitaxy and some dopant can be added during theepitaxial growth. Then, another oxide layer 8 is formed atop the siliconlayer 7.

The structure comprising the donor substrate 1 and the silicon substrate5 are then bonded to each other at the free surfaces of the oxide layers4 and 8 as it is indicated by the arrow in FIG. 1. Next, stresses, forexample, thermal and/or mechanical stresses are applied to the bondedstructure in order to detach the donor substrate 1 and the nucleationlayer 2. For this, the Smart Cut© process may be employed, i.e., a heattreatment is carried out at a temperature of about 500° C. to 600° C.,for a time period of about 30 minutes up to about 3 hours, for example.Alternatively, a laser lift-off technique that is also known in the artmay be applied in order to detach the donor substrate 1.

After detachment and a surface treatment like grinding and/orchemical-mechanical polishing the wafer results that is illustrated inthe lower sketch of FIG. 1. On the silicon substrate 5 it is arrangedthe doped layer 6. On the doped layer 6 it is arranged the first(intrinsic) silicon layer 7. On the silicon layer 7 it is arranged aburied oxide layer 9 resulting from the bonded oxide layers 4 and 8. Onthe buried oxide layer 9 it is arranged the second silicon layer 3.Exemplary thicknesses of the individual layers of the wafer are asfollows. The doped layer 6 may have a thickness of some μm, for example,2 to 5 μm. The (intrinsic) silicon layer 7 may have a thickness of some50 nm. The buried oxide layer 9 may have a thickness of 5 to 25 nm andthe top silicon layer 3 may have a thickness of 5 to 20 nm.

In FIG. 2 an embedded DRAM device in a DRAM part A integrated with SOItransistors of a logic part B for addressing the DRAMs manufactured bymeans of the wafer shown in FIG. 1 is illustrated. On the left-hand-sidethe DRAM part A is illustrated and on the right-hand side of FIG. 2 thelogic part B is illustrated. In the DRAM part A a capacitor deep trench10 extending to the doped layer 6 that functions as a capacitor backplate is illustrated. A control FET 11 is formed in the DRAM part A witha channel region formed in the upper silicon layer 3. The control FET 11may be realized as a fully depleted or partially depleted device. Thethickness of the upper silicon layer 3 is chosen accordingly.

The DRAM part A and the logic part B are separated from each other by ashallow trench isolation 12. Transistors 13 formed in the logic part Bare also separated from each other by shallow trench isolation 12.Regions of the silicon layer 7 can be easily converted into dopedregions in order to form back-biasing regions for the transistors 13.For example, a region of the silicon layer 7 below the left transistor13 in the logic part B may be n doped with a concentration of some 10¹⁸cm⁻³ whereas a region of the silicon layer 7 below the right transistor13 in the logic part B may be p doped with a concentration of some 10¹⁸cm⁻³ depending on the Vt shift we want to induce in the transistorchannels formed in the upper silicon layer 3. FIG. 2, moreover, showscontacts 14 for back-biasing. N back-biasing regions in the logic part Bare connected with each other through the n⁺ doped doped layer 6. Inorder to ensure sufficient electrical resistivity between twoback-biasing contacts it might be considered necessary to keep some partof the intrinsic silicon layer 7 undoped or p doped. Thus, the intrinsicsilicon layer 7 might be provided with a thickness of some 100 to 300nm.

It should be noted that the shallow trench isolators 12 might beprovided extending partly into the doped layer 6. They might also beprovided extending through the doped layer 6 and into the substrate 5thereby cutting the n⁺ doped layer 6, Different embedded DRAM blocks canbe separated by such shallow trench isolators 12 reaching into thesubstrate 5.

All previously discussed embodiments are not intended as limitations butserve as examples illustrating features and advantages of the invention.It is to be understood that some or ail of the above described featurescan also be combined in different ways.

1. A method for the manufacture of a wafer, which comprises: providing adoped layer on a semiconductor substrate; providing a firstsemiconductor layer on the doped layer; providing an oxide layer on thefirst semiconductor layer; and providing a second semiconductor layer onthe oxide layer to form a wafer having a buried oxide layer and a dopedlayer beneath the buried oxide layer.
 2. The method according to claim1, wherein the doped layer and the first semiconductor layer provided bybeing grown on the semiconductor substrate.
 3. The method according toclaim 1, wherein the second semiconductor layer is provided by firstbeing grown on a donor substrate followed by bonding of thesemiconductor layer and donor substrate to the oxide layer of thesemiconductor substrate.
 4. The method according to claim 3, wherein thewafer is obtained by detaching the donor substrate to transfer thesecond semiconductor layer to the semiconductor substrate.
 5. The methodaccording to claim 3, wherein the oxide layer is provided on the firstsemiconductor layer or on the second semiconductor layer, or on bothsemiconductor layers prior to bonding.
 6. The method according to claim1, wherein the doped layer is provided by epitaxial growth of a dopedlayer on the semiconductor substrate; and the first semiconductor layeris provided by epitaxial growth of the semiconductor layer on the dopedlayer.
 7. The method according to claim 6, wherein the secondsemiconductor layer is provided on the buried oxide layer by: growingthe second semiconductor layer on a donor substrate to obtain a donorwafer; or forming an oxide layer on either the second semiconductorlayer grown on the donor substrate, or on the epitaxial firstsemiconductor layer grown on the doped layer; or on both layers; andbonding the donor wafer to the first semiconductor layer by the oxidelayer or layers, and detaching the donor substrate to transfer thesecond semiconductor layer to the semiconductor substrate.
 8. The methodaccording to claim 1, wherein the doped layer is provided by doping atleast a region of the first semiconductor layer by n or p dopants.
 9. Amethod for the manufacture of a semiconductor device, which comprises:providing a wafer obtained by the method according to claim 1; formingan embedded DRAM device in a first region of the wafer; and forming aback-biased transistor in a second region of the wafer that is differentfrom the first region.
 10. The method according to claim 9, wherein theforming of the embedded DRAM device in the first region of the wafercomprises forming a capacitor trench extending from the secondsemiconductor layer at least partly into the doped layer.
 11. The methodaccording to claim 9, wherein the back-biased transistor in the secondregion of the wafer is separated from the first region by providing ashallow trench isolator therebetween when forming a back-biasing regionin the first semiconductor layer.
 12. The method according to claim 11,wherein the forming of the back-biasing region in the firstsemiconductor layer comprises doping at least a part of the firstsemiconductor layer of the already provided wafer with n or p dopants.13. A wafer comprising: a semiconductor substrate; a doped layer uponthe semiconductor substrate; a first semiconductor layer upon the dopedlayer of the semiconductor substrate; an oxide layer upon the firstsemiconductor layer; and a second semiconductor layer formed upon theoxide layer; thus providing a wafer having a buried oxide layer and adoped layer beneath the buried oxide layer.
 14. The wafer according toclaim 13, wherein one or more of the semiconductor substrate, the firstsemiconductor layer or the second semiconductor layer comprises orconsists of silicon.
 15. The wafer according to claim 13, wherein thedoped layer comprises n or p dopants.
 16. The wafer according to claim13, which includes one or more of the following features: the firstsemiconductor layer has a thickness of 10 to 300 nm; or the secondsemiconductor layer has a thickness of 5 to 100 nm; or the buried oxidelayer has a thickness of 10 to 200 nm; or the doped layer has athickness of 1 to 10 μm.
 17. The wafer according to claim 13, whichincludes one or more of the following features: the first semiconductorlayer has a thickness of 50 to 150 nm; or the second semiconductor layerhas a thickness of 5 to 15 nm; or the buried oxide layer has a thicknessof 5 to 25 nm; or the doped layer has a thickness of 1 to 10 μm.
 18. Asemiconductor device, comprising: a wafer according to claim 13; andintegrated on that wafer an embedded DRAM device comprising a capacitortrench extending from the second semiconductor layer at least partlyinto the doped layer and a control HT having a channel region in thesecond semiconductor layer; and a back-biased SOI transistor comprisinga channel region in the second semiconductor layer and a dopedback-biasing region in the first semiconductor layer and a contact forcontacting the doped back-biasing region.
 19. The semiconductor deviceaccording to claim 18, wherein the first semiconductor layer is doped inan upper region adjacent to the buried oxide layer and undoped in alower region adjacent to the doped layer.
 20. The semiconductor deviceaccording to claim 18, comprising a number of back-biased SOItransistors separated from each other and from the embedded DRAM deviceby shallow trench isolators extending from the second semiconductorlayer at least partly into the doped layer or through the doped layerinto the semiconductor substrate.